The use of scan test methodology requires the control of clock pins on scan registers within the programmable IC from external package pins. (Scan test methodology is well known in the art and therefore is not described in detail herein. The term "programmable IC" as used herein includes but is not limited to FPGAs, mask programmable devices such as Application Specific ICs (ASICs), Programmable Logic Devices (PLDs), and devices in which only a portion of the logic is programmable.) If the design implemented in the programmable IC contains internally generated clocks, multiplexers (MUXes) are added to disable the internally generated clocks and feed the scan test clock to the scan registers during testing. The addition of MUXes and scan clock skew caused by different routing delays makes it difficult to clock all the scan registers in a synchronized manner. "Clock skew" is defined as the maximum time difference between arrival times of a clock edge at clock pins of multiple registers. As a result of clock skew, a transition in one register can occur within the set-up or hold time window of another register, thereby causing timing errors.
The terms "set-up time" and "hold time" describe the timing requirements on the data input signal of a flip-flop or register with respect to the clock input signal. The set-up time is the amount of time that the input data must be present at the data pin of the register prior to an active clock edge. The hold time is the amount of time that the input data must remain at the data pin of the register after the active clock edge. Therefore, the set-up and hold times describe a window of time during which data must be stable in order to guarantee predictable performance over the full range of operating conditions and manufacturing tolerances.
Test vectors for an IC are usually generated using an automated test pattern generator (ATPG) tool. Currently available ATPG tools assume an ideal clock, i.e., they assume there is no clock skew on the scan test clock. Therefore, typically the only way to make the test vectors simulate and function correctly on the tester is to reduce the clock skew by iterative placement, routing, and back annotated simulation. In other words, the design must be implemented many times in an attempt to find one implementation with sufficiently small clock skew that the scan testing functions correctly. This process can be very time consuming for an IC of even moderate complexity, causing long delays in the design cycle.
FIG. 1A shows an example of the circuit typically used in programmable IC scan logic. The scan circuit 10 includes a plurality of registers 12a, 12b, 12c, and 12d typically comprising variously sized sets of flip-flops (as shown) as well as other logic elements (not shown). Clock signals CLKA, CLKB, CLKC, and CLKD are separately applied to registers 12a-12d, respectively.
Under ordinary operating conditions (i.e., in user mode), a package pin 16 (i.e., a pin external to the IC package) is supplied with an externally generated primary clock signal, which is applied through a MUX 22 to register 12aas the clock signal CLKA. During scan testing, however, an externally generated test clock is applied to a package pin 18 which is connected through MUX 22 to register 12a. The test clock is also supplied from package pin 18 through an optional delay element 30 and a MUX 24 to register 12b, and also through an optional delay element 32 and a MUX 26 to register 12c. The test clock is further supplied from package pin 18 through two optional delay elements 34, 36 in series and a MUX 28 to the flip-flop set 12d. These and other delay elements in FIG. 1A represent the routing delays on the scan clock path resulting, for example, from the placement and routing of a design in a programmable IC. Delay elements may also be included in the form of buffers or delay cells.
Also, a first internally generated clock (internal clock) is applied through MUX 24 to register 12b, a second internal clock is applied through MUX 26 to register 12c, and an externally generated auxiliary clock (Aux. clock) supplied at package pin 20 is applied through MUX 28 to register 12d.
Under scan test conditions (i.e., in test mode), MUXes 22, 24, 26, 28 are supplied with a test mode control signal TM that causes the primary clock, the internal clocks, and the auxiliary clock to be disconnected from registers 12a-12d, and the test clock to be connected to registers 12a-12d.
Since the number of flip-flops in each of registers 12a-12dmay be different, the loading on each of clock signals CLKA-CLKD may also be different. This difference in loading coupled with differences in routing delays causes the arrival time of the test clock signal applied to package pin 18 to be different for each of registers 12a-12d. The presence of delay elements 30, 32, 34, and 36 demonstrates an attempt to balance the delay on the clock paths. The values of these delay elements are typically iteratively adjusted to make the arrival time of CLKA-CLKD the same for each register. The ideal test vectors generated by the ATPG tools assume equal total delay on each of the various paths from the test clock pin to the registers.
FIG. 1B shows a timing diagram for scan circuit 10 of FIG. 1A. Clearly, for a given Test Clock pulse applied to external pin 18, the actual arrival time of the clock pulse to destination flip-flops clocked by clock signals CLKA, CLKB, CLKC, and CLKD are different. This result is due to inter-clock skew caused by variable loading and differences in routing delays.
FIG. 2 is a timing diagram that shows how these differing delays can cause set-up and hold violations. Trace 201 shows a clock pulse at the clock pin of register 12a(CLKA). Trace 202 shows the transition on the output signal from register 12a. Note that there is a delay (the delay through one flip-flop, in this case) between the rising edge of clock signal CLKA and the transition in trace 202. Vertical dashed lines 38 define the set-up and hold window for register 12b (clocked by clock signal CLKB, trace 203). Trace 202 shows that the transition caused by clock signal CLKA falls inside the set-up and hold window 38 for the register clocked by clock signal CLKB, due to skew between clock signals CLKA and CLKB. This transition therefore causes a timing error whenever a signal driven by register 12aprovides data to register 12b. The timing error may cause erroneous data to be captured by register 12b. Such timing errors are typically reported when ATPG vectors are simulated using a simulation tool. These timing errors must each be carefully evaluated to determine the cause, and the circuit must be adjusted to eliminate the errors.
Conventionally, a timing error is fixed by eliminating the skew between clock signals CLKA and CLKB by changing the values of the delay elements, which involves the time-consuming process of iterating the placement and routing process until satisfactory delays are achieved. Trace 204 of FIG. 2 shows an adjusted CLKB clock pulse, where appropriate delays have been inserted in the clock paths to balance the delays between CLKA and CLKB. Note that the transition caused by CLKA is now outside of set-up and hold window 205 for adjusted CLKB. This "trial and error" method is inefficient. Therefore, it is desirable to provide a method for scan testing that eliminates timing errors without iterative placement and routing.